Clock control system

ABSTRACT

To save power by supplying minimum clocks required for respective blocks. In a clock control system that supplies clocks to a plurality of blocks such as a CPU  4 , a bus  5 , a peripheral circuit  6  and other circuits  7 , a clock supplied from a clock oscillator  1  is supplied to clock control sections  8 a,  8 b,  8 c and  8 d that are connected to the blocks  4, 5, 6  and  7 , respectively, wherein the clock is converted by the clock control sections  8 a,  8 b,  8 c and  8 d into clocks with minimum clock numbers required for operating the blocks  4, 5, 6  and  7 , respectively, and supplied to the blocks  4, 5, 6  and  7.

BACKGROUND OF THE INVENTION

[0001] 1. Field of Invention

[0002] The present invention relates to a clock control system thatsupplies clocks to each block in a microcomputer or the like.

[0003] 2. Description of Related Art

[0004]FIG. 4 shows a conventional clock frequency divider system.

[0005] The figure shows a clock oscillator 1, a frequency dividercircuit 2 and a microcomputer 3 that is equipped with blocks such as aCPU 4, a bus 5, a peripheral circuit 6 and other circuits 7. A clockprovided by the clock oscillator 1 is first divided by the frequencydivider circuit 2, and the clock divided at a specified ratio issupplied to each of the blocks 4 through 7.

[0006] In the system described above in which a single clock from thecommon frequency divider circuit 2 is supplied to all of the blocks 4through 7, the same clock that is supplied to a block that requires ahigh clock number such as the CPU 4 is also supplied to the other blocksthat may require low clock numbers such as the bus 5, the peripheralcircuit 6 and the like. In recent years, power saving is demanded inevery equipment, but the conventional system such as the one describedabove has a problem because it supplies unnecessary clock numbers, andtherefore cannot reduce the power consumption through minimum clock thatis required for each of the blocks.

[0007] The present invention has been made to solve the problemsdescribed above, and its object is to provide a clock control systemthat improves power saving by supplying a minimum clock required foreach block.

SUMMARY OF THE INVENTION

[0008] To solve the problems described above, the present invention ischaracterized in that, in a clock control system that supplies a clockoscillated by a clock oscillator to a plurality of blocks, the clockcontrol system includes: a plurality of clock control sections that aresupplied with the clock oscillated by the clock oscillator; and aplurality of blocks connected to the clock control sections,respectively, wherein the clock supplied from the clock oscillator isconverted by each of the clock control sections to a clock with aminimum clock number required for operating each of the correspondingrespective blocks and supplied to each of the corresponding respectiveblocks.

[0009] The present invention is characterized in that each of the clockcontrol sections is composed of a counter that counts the clock of theclock oscillator, a frequency dividing ratio setting section that sets afrequency dividing ratio, and a comparison section that compares outputsof the counter and the frequency dividing ratio setting section andoutputs a divided clock that is set by the frequency dividing ratiosetting section.

[0010] The present invention is characterized in comprising a latchcircuit that receives inputs of the clock supplied from the clockoscillator and the clock supplied from the comparison section, and anAND circuit that provides a logical product of the clock supplied fromthe clock oscillator and the clock supplied from the latch circuit andsupplies the logical product to each of the corresponding respectiveblocks.

[0011] The present invention is characterized in that, in a clockcontrol system that supplies a clock oscillated by a clock oscillator toa plurality of blocks, the clock control system comprises: supplying theclock supplied from the clock oscillator to a frequency divider circuitthat is connected to each of the blocks, and controlling the frequencydivider circuit by a CPU to convert the clock to a clock with a minimumclock number required for operating each of the corresponding respectiveblocks and supply the clock to each of the corresponding respectiveblocks.

[0012] The present invention is characterized in that, in a clockcontrol system that supplies a clock oscillated by a clock oscillator toa plurality of blocks, the clock control system comprises: supplying theclock supplied from the clock oscillator to a clock stop section that isconnected to each of the blocks, and controlling the clock stop sectionby a CPU to stop supplying the clock to any of the blocks that do notneed the clock.

[0013] In the clock control system that supplies a clock to theplurality of blocks, the present invention is characterized in that theclock stop section is equipped with an AND circuit that is connected toeach of the blocks and receives an input of the clock of the clockoscillator and a flip-flop that provides an input signal to the ANDcircuit, wherein the flip-flop is controlled by a CPU to turn on or offoutputting the clock from the AND circuit, and the present invention ischaracterized in supplying the clock supplied from the clock oscillatorto a clock control section that is connected to each of the blocks,converting with the clock control section the clock to a clock with aminimum clock number required for operating each of the correspondingrespective blocks and supplying the clock to each of the correspondingrespective blocks.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 shows a block diagram of a clock control system inaccordance with a first embodiment of the present invention.

[0015]FIG. 2 shows a block diagram of a clock control system inaccordance with a second embodiment of the present invention.

[0016]FIG. 3 shows a block diagram of a clock control system inaccordance with a third embodiment of the present invention.

[0017]FIG. 4 shows a block diagram of a conventional clock controlsystem.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0018] A clock control system in accordance with embodiments of thepresent invention is described below with reference to the accompanyingdrawings.

[0019]FIG. 1 shows a clock control system in accordance with a firstembodiment of the present invention. It is noted that components in thefigure that are the same components as shown in FIG. 4 or have thosehaving the same functions are assigned the same reference numerals.

[0020] The figure shows clock control sections 8 a, 8 b, 8 c and 8 dthat are connected to blocks comprising a CPU 4, a bus 5, a peripheralcircuit 6 and another circuit 7, respectively. Each of the clock controlsections is composed of a counter 9 that counts a clock from a clockoscillator 1, a frequency dividing ratio setting section 10 that sets afrequency dividing ratio, and a comparison section 11 that compares theclock number of the counter 9 with the frequency dividing ratio settingsection 10 and converts the clock of the counter 9 into a clock numberthat is set by the frequency dividing ratio setting section 10.Reference numeral 17 denotes latch circuits 17 that each receive anoutput from the comparison section 11 and an input of the clock from theclock oscillator 1. An output of the latch circuit 17 and a clock of theclock oscillator 1 are inputted in an AND circuit 18, and the ANDcircuits provide outputs to the blocks 4, 5, 6 and 7, respectively.

[0021] Next, operations are described.

[0022] Each of the frequency dividing ratio setting sections 10 in therespective clock control sections 8 a, 8 b, 8 c and 8 d sets an optimumclock frequency dividing ratio for each of the corresponding blocks 4through 7. For example, when the clock control section 8 a for the CPU 4is set at a clock frequency dividing ratio of {fraction (1/1)}, theclock control section 8 b for the bus 5 is set at ¼, the clock controlsection 8 c for the peripheral circuit 6 is set at ½, and the clockcontrol section 8 d for the other circuit 7 is set at ¼. As a result,the comparison circuits 11 output divided clocks that are 1, ¼, ½ and ¼of the clock number of the clock oscillator 1, respectively, which areinputted in the latch circuits 17, respectively.

[0023] When a low output from the comparison circuit 11 is inputted inthe latch circuit 17, the latch circuit 17 does not provide an output,and an output of the AND circuit 18 is “0”; in this case, no clocksignal is inputted in the blocks, i.e., the CPU 4, the bus 5, theperipheral circuit 6 or the other circuit 7. When a high output from thecomparison circuit 11 is inputted in the latch circuit 17, the latchcircuit 17 provides an output, such that an output of the AND circuit 18is “1”; in this case, the clock signal is inputted in the blocks, i.e.,the CPU 4, the bus 5, the peripheral circuit 6 and the other circuit 7.In this manner, an optimum clock can be supplied to each of the blocks 4through 7 through setting an optional clock frequency dividing ratio byeach of the respective frequency dividing ratio setting sections 10, andunnecessary clocks do not have to be supplied. As a result, lower powerand power saving can be attained.

[0024]FIG. 2 shows a clock control system in accordance with a secondembodiment of the present invention.

[0025] As indicated in the figure, frequency divider circuits 12 a, 12b, 12 c and 12 d are provided between a clock oscillator 1 and blocks,such as, a CPU 1, a bus 5, a peripheral circuit 6 and another circuit 7,respectively, and frequency dividing ratios of the respective frequencydivider circuits 12 a, 12 b, 12 c and 12 d are varied by softwarecontrols by the CPU 4.

[0026] In the second embodiment also, like the first embodiment,

[0027] an optimum clock can be supplied to each of the blocks 4 through7, and unnecessary clocks do not have to be supplied, such that lowerpower and power saving can be attained. Also, due to the fact that theCPU 4 in which the clock is supplied can be used for the softwarecontrol of the frequency divider circuits 12 a through 12 d, thestructure becomes simpler.

[0028]FIG. 3 shows a clock control system in accordance with a thirdembodiment of the present invention.

[0029] As indicated in the figure, a clock stop section 13 is providedbetween a clock oscillator 1 and blocks such as a CPU 4, a bus 5, aperipheral circuit 6 and another circuit 7. The clock stop section 13 isequipped with AND circuits 14 provided between the clock oscillator 1and the respective blocks 4 through 7, and flip-flops 15 that outputclock pulses to the corresponding respective AND circuits 14. Each ofthe AND circuits 14 provides a logical product of outputs of the clockoscillator 1 and each of the corresponding flip-flops 15 to each of theblocks 4 through 7. Each of the flip-flops 15 can be read/written by thesoftware control of the CPU 4 to thereby turn on and off the output ofeach of the corresponding AND circuits 14, respectively.

[0030] In the third embodiment, clocks are supplied to any of the blocksthat require the clocks, and clocks are stopped to those of the blocksthat do not require the clocks. As a result, a finer clock controlbecomes possible and unnecessary clocks do not have to be supplied, suchthat the power can be lowered and power saving can be achieved. Also,due to the fact that the CPU 4 in which the clock is supplied can beused for the software control of the flip-flops 15, the structurebecomes simpler.

[0031] As described above, in accordance with the present invention, aclock supplied from a clock oscillator is converted by clock controlsections into clocks with minimum clock numbers that are required forrespective blocks and supplied to the respective blocks, such that anoptimum clock can be supplied to each of the blocks; also unnecessaryclocks do not have to be supplied. Accordingly, the invention iseffective in saving the power.

[0032] Also, in accordance with the present invention, a clock suppliedfrom a clock oscillator is supplied to frequency divider circuits thatare connected to respective blocks, and the frequency divider circuitsare controlled by a CPU such that minimum frequencies required for therespective blocks are supplied. Accordingly, the invention is effectivein composing the system with a simple structure due to the fact that thefrequency divided clocks can be controlled by the software control ofthe CPU.

[0033] Also, in accordance with the present invention, a clock stopsection may stop supplying a clock supplied from a clock oscillator tounnecessary blocks. As a result, a finer clock control becomes possibleand unnecessary clocks do not have to be supplied, such that the powercan be lowered and power saving can be achieved.

What is claimed is:
 1. A clock control system that supplies a clock oscillated by a clock oscillator to a plurality of blocks, the clock control system characterized in comprising: a plurality of clock control sections that are supplied with the clock oscillated by the clock oscillator; and a plurality of blocks connected to the clock control sections, respectively, wherein the clock supplied from the clock oscillator is converted by each of the clock control sections to a clock with a minimum clock number required for operating each of the corresponding respective blocks and supplied to each of the corresponding respective blocks.
 2. A clock control system according to claim 1, wherein each of the clock control sections is composed of a counter that counts the clock of the clock oscillator, a frequency dividing ratio setting section that sets a frequency dividing ratio, and a comparison section that compares outputs of the counter and the frequency dividing ratio setting section and outputs a divided clock that is set by the frequency dividing ratio setting section.
 3. A clock control system according to claim 1, further comprising a latch circuit that receives inputs of the clock supplied from the clock oscillator and the clock supplied from the comparison section, and an AND circuit that provides a logical product of the clock supplied from the clock oscillator and the clock supplied from the latch circuit and supplies the logical product to each of the corresponding respective blocks.
 4. A clock control system that supplies a clock oscillated by a clock oscillator to a plurality of blocks, the clock control system characterized in comprising: supplying the clock supplied from the clock oscillator to a frequency divider circuit that is connected to each of the blocks, and controlling the frequency divider circuit by a CPU to convert the clock to a clock with a minimum clock number required for operating each of the corresponding respective blocks and supply the clock to each of the corresponding respective blocks.
 5. A clock control system that supplies a clock oscillated by a clock oscillator to a plurality of blocks, the clock control system characterized in comprising: supplying the clock supplied from the clock oscillator to a clock stop section that is connected to each of the blocks, and controlling the clock stop section by a CPU to stop supplying the clock to any of the blocks that do not need the clock.
 6. A clock control system according to claim 5, wherein the clock stop section is equipped with an AND circuit that is connected to each of the blocks and receives an input of the clock of the clock oscillator and a flip-flop that provides an input signal to the AND circuit, wherein the flip-flop is controlled by a CPU to turn on or off outputting the clock from the AND circuit. 